DLD-Quiz-Module4

What is the value of the register formed from D flipflops using $$Q_0$$ , $$Q_1$$ and $$Q_2$$ as output $$Q_0Q_1Q_2$$ after 14 cycles. Initial output is 000

A three bit pseudo random number generator is shown. Initially the value of output Y= $$Y_2Y_1Y_0$$ is set to 111. The value of output Y after three clock cycles is

A bidirectional 4-bit shift left register is storing the nibble 1110. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing

Modulus refers to ____________

The minimum number of flip-flops that can be used to construct a modulus-5 counter is ____________

A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________

he group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________

On the fifth clock pulse, a 4-bit Johnson sequence is Q₀ = 0, Q₁ = 1, Q₂ = 1, and Q₃ = 1. On the sixth clock pulse, the sequence is ________.

A MOD-16 ripple counter is holding the count 1001. What will the count be after 31 clock pulses?

A state diagram is a table of states.