Verilog Fundamentals
Authored by Kumar Khandagle
Professional Development
Professional Development
Used 86+ times
AI Actions
Add similar questions
Adjust reading levels
Convert to real-world scenario
Translate activity
More...
Content View
Student View
15 questions
Show all answers
1.
MULTIPLE CHOICE QUESTION
1 min • 1 pt
initial statement is
Synthesizable
Not Synthesizable
2.
MULTIPLE CHOICE QUESTION
1 min • 1 pt
always construct is Synthesizable
True
False
3.
MULTIPLE CHOICE QUESTION
1 min • 1 pt
#5 is Synthesizable
True
False
4.
MULTIPLE CHOICE QUESTION
1 min • 1 pt
= and <= represent
Non-blocking and Blocking Assingment respectively
Blocking and Non-blocking Assingment respectively
5.
MULTIPLE CHOICE QUESTION
1 min • 1 pt
Verilog is an
Case Insensitive
Case Sensitive
Can't say
6.
MULTIPLE CHOICE QUESTION
1 min • 1 pt
Integer datatype is allocated ______ number of bits
16
32
64
8
7.
MULTIPLE CHOICE QUESTION
1 min • 1 pt
reg [4:1] pwm will initialize variable of _______ bits
3
4
5
6
Access all questions and much more by creating a free account
Create resources
Host any resource
Get auto-graded reports
Continue with Google
Continue with Email
Continue with Microsoft
or continue with
%20(1).png)
Apple
Others
Already have an account?
