H CS - Computer structure

What is missing from step 2 of the fetch-execute cycle?

1.The MAR sets up the address bus with the memory location to be read from.

2.The ____ ____ on the control unit is activated by the processor.

3.The data from the memory address is placed on the data bus and transferred back to the instruction register.

4.The instruction in the instruction register is then interpreted by the decoder and carried out.

Which component is missing from step 1 of the fetch-execute cycle?

1.The

Which component is missing from step 3 of the fetch-execute cycle?

1.The MAR sets up the address bus with the memory location to be read from.

2.The read line on the control unit is activated by the processor.

3.The data from the memory address is placed on the ____ ___ and transferred back to the instruction register.

4.The instruction in the instruction register is then interpreted by the decoder and carried out.