Lesson aims and success criteria

Learning intentions

• Describe the concept of the fetch-execute cycle.

Success Criteria

• I can recall the steps of memory read and write cycle.

The fetch-execute cycle

The term fetch/execute cycle is used to describe the process of sending and receiving data to/from the processor and memory (whether it be RAM (main memory) or cache).

During the fetch/execute cycle the Control Unit, Registers, Data Bus, and Address Bus are all in use.

The control unit will dictate the clock speed of the fetch/execute cycle as well as activating either the read or write line.

The control unit

The control unit does not carry any data in the way that a data bus does but it has a number of lines that perform particular tasks, these are detailed below.

• Clock - Generates a constant pulse (measured in Mhz/Ghz). One operation will be carried out per core per pulse.

• Reset - Returns the system/CPU/processor to its initial state saves contents and clears registers. This is not the same as resetting the power.

• Interrupt - Notifies the processor that an external event has occurred such as I/O from a device. This type of interrupt can be ignored.

• Non Maskable Interrupt (NMI) - This is an interrupt that CANNOT be ignored such as a low power failure notification.

Memory Read operation

1. MAR (Memory Address Register) sets up the address bus with the relevant memory location to be read from

2. The control unit read line is activated

3. The contents of the address held on the address bus are placed on the data bus

4. The data bus transfers the data from memory to the MDR (Memory Data Register)

5. The instruction is decoded and executed

Memory Write operation

1. MAR (Memory Address Register) sets up the address bus with the relevant memory location to be written to

2. MDR (Memory Data Register) passes the data to be written to the data bus

3. The control unit write line is activated

4. The data bus transfers the data to the memory location specified on the address bus