Asynchronous and Synchronous Counters
Presentation
•
Other
•
9th - 12th Grade
•
Medium
Jennifer Fenn
Used 10+ times
FREE Resource
7 Slides • 5 Questions
1
Output is free from the clock signal
Supplied with different clock signals, there may be delay in producing output.
The clock inputs of all flip flops are cascaded and the D input of each flip flop is connected to a state output of the flip flop.
The flip flop will toggle at each active edge or positive edge of the clock signal.
The clock input from Q' output of the previous flip flop.
2
All flip -flops are simultaneously clocked by and external clock.
Synchronous counters are faster than asynchronous counters.
Synchronous counters do not suffer from the ripple effect that asynchronous counters do.
They require more logic.
3
2.) Notice the difference between these two.
3.)
4
2.) Label the count (at the bottom
3.) Add dotted lines between pulses starting from pulses down to align with the count at the bottom.
5
6
Multiple Choice
What is happening with Q0? (red arrows)
Toggles on Falling Edge of CLOCK & Q0 = 1
Toggles on Falling Edge of CLOCK
Toggles on Falling Edge of CLOCK & Q0 = 1 & Q1 = 1
Nothing, it remains low all the time.
7
Multiple Choice
What is happening with Q1? (purple arrows)
Toggles on Falling Edge of CLOCK & Q0 = 1
Toggles on Falling Edge of CLOCK
Toggles on Falling Edge of CLOCK & Q0 = 1 & Q1 = 1
Nothing, it remains low all the time.
8
Multiple Choice
What is happening with Q2? (green arrows)
Toggles on Falling Edge of CLOCK & Q0 = 1
Toggles on Falling Edge of CLOCK
Toggles on Falling Edge of CLOCK & Q0 = 1 & Q1 = 1
9
10
2.) Circle the external clock.
11
Multiple Choice
Ripple counters are also called ______?
SSI Counter
Asynchronous counters
Synchronous counters
mode counter
12
Multiple Choice
A ring counter with 5 flip flops will have ____ states,
5
10
32
12
Output is free from the clock signal
Supplied with different clock signals, there may be delay in producing output.
The clock inputs of all flip flops are cascaded and the D input of each flip flop is connected to a state output of the flip flop.
The flip flop will toggle at each active edge or positive edge of the clock signal.
The clock input from Q' output of the previous flip flop.
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